The design of an integrated circuit (IC) is an extremely complicated task and requires a structured approach. Generally, the IC design flow can be broken down into the steps of implementation and verification. Implementation usually involves the creation of a specification, an RTL model, a transistor-level model, or a gate-level netlist. Verification is usually performed by simulators that test the functionality of an IC in a software environment before creation of a physical prototype. To perform such testing, simulators predict the behavior of a system by using mathematical models of the system components. Based on the circuit signals, different types of simulators are chosen to perform the simulation, such as digital, analog, and RF simulators.
For digital simulation, the modeling begins with a software program that describes the behavior or functionality of a circuit. This software program is written in a hardware description language (HDL) that defines an algorithm to be performed with limited implementation details. Designers direct behavioral synthesis tools to generate alternate architectures by modifying constraints (such as clock period, number and type of data path elements, and desired number of clock cycles). Behavioral synthesis tools convert the HDL program into a register transfer level (RTL) description, which is used for simulation. The RTL description is used to ultimately generate a netlist that includes a list of components in the circuit and the interconnections between the components. This netlist is used to create the physical integrated circuit. Digital simulation usually relates to events where data changes on clock cycles and the logical voltage levels are limited to two or three.
Analog simulation is used for DC, AC and transient analyses and operates on a transistor-level description, which is a full netlist of the physical circuit containing detailed architectural and parasitic information. Analog behavioral languages (e.g., Verilog-AMS or VHDL-AMS) also exist and allow the user to model an analog design at a higher level of abstraction. The analog design process includes the creation of schematics, layout, and extraction resulting in the netlist used for simulation. The analog simulator (e.g., SPICE) uses the netlist as an input to formulate non-linear equations for the circuit to solve for the unknown waveform V(t). Iterative methods, such as Newton-Raphson, can be used to solve these non-linear systems of equations. For transient analysis, most analog simulators choose time points at which the system is solved in order to meet a desired accuracy criteria. Thus the basic difference between analog and digital simulators is that an analog simulator considers the voltages and currents in a circuit to be continuous quantities, rather than quantized into high/low values, as in digital. This allows analog simulators to calculate voltage and current as a function of time.
RF simulators perform both steady-state analysis and modulated steady-state analysis (also called envelope analysis). The steady state is defined as the state when all initial transients have vanished, and the circuit operates with periodic or quasi-periodic large signals. There exists two types of algorithms to compute steady state: the Shooting algorithm in the time domain and the Harmonic Balance algorithm in the frequency domain. Modulated steady-state analysis is an algorithm dedicated to the simulation of circuits stimulated by (non periodic) modulated signals. It efficiently handles the modulation information carried by RF signals. The output of the modulated steady-state analysis is a time-varying spectrum. An example use of RF simulators is for RF transceivers found in mobile phones. These circuits include low noise amplifiers, mixers, filters, oscillators etc., which operate in a RF frequency range (e.g., typically from a few 100 MHz to 5 GHz).
However, a problem exists with analog and RF simulation. It is desirable to increase the speed of the simulation, but maintain accuracy. Existing techniques for increasing speed, sacrifice accuracy and existing techniques for increasing accuracy, substantially slow the speed. For example, to increase accuracy it is possible to include parasitic information into the simulation. Parasitic information relates to elements not included in the original netlist, but are added due to layout and extraction. For example, two electrical paths placed in close proximity during layout will generate a coupling capacitor during extraction. Such a coupling capacitor was not present in the original netlist, but was added because of the physical layout of the circuit. Such parasitic information may include resistors, inductors, capacitors, etc. Generally, the parasitic information makes the matrices used during simulation much larger and denser slowing the simulation time substantially. There are a number of prior-art techniques for reducing parasitic information, such as “circuit simplification” and “reduced order modeling”. Circuit simplification simply removes parasitic information from the circuit description to speed up simulation. The parasitic information may be listed in the circuit netlist or in a separate file (e.g., a DSPF) and, once identified, can simply be deleted from the circuit description. “Reduced order modeling” reduces parasitics by building a model of the parasitics imitating their functional behavior but in a simplified and more compact form. While removing, reducing, or modeling the parasitic information does make factorization simpler, it sacrifices the accuracy of the simulation. For example, even though the parasitic information often relates to components that are less significant in the simulation, their removal does modify the ultimate solution.
Thus, it is desirable to reconcile the competing interests of increasing the speed of circuit simulation, while obtaining a high level of simulation accuracy that incorporates parasitic elements.